269 lines
8.6 KiB
Python
269 lines
8.6 KiB
Python
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from _sx126x import *
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from sx126x import SX126X
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_SX126X_PA_CONFIG_SX1262 = const(0x00)
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class SX1262(SX126X):
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TX_DONE = SX126X_IRQ_TX_DONE
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RX_DONE = SX126X_IRQ_RX_DONE
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ADDR_FILT_OFF = SX126X_GFSK_ADDRESS_FILT_OFF
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ADDR_FILT_NODE = SX126X_GFSK_ADDRESS_FILT_NODE
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ADDR_FILT_NODE_BROAD = SX126X_GFSK_ADDRESS_FILT_NODE_BROADCAST
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PREAMBLE_DETECT_OFF = SX126X_GFSK_PREAMBLE_DETECT_OFF
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PREAMBLE_DETECT_8 = SX126X_GFSK_PREAMBLE_DETECT_8
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PREAMBLE_DETECT_16 = SX126X_GFSK_PREAMBLE_DETECT_16
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PREAMBLE_DETECT_24 = SX126X_GFSK_PREAMBLE_DETECT_24
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PREAMBLE_DETECT_32 = SX126X_GFSK_PREAMBLE_DETECT_32
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STATUS = ERROR
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def __init__(self, spi_bus, clk, mosi, miso, cs, irq, rst, gpio):
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super().__init__(spi_bus, clk, mosi, miso, cs, irq, rst, gpio)
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self._callbackFunction = self._dummyFunction
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def begin(self, freq=434.0, bw=125.0, sf=9, cr=7, syncWord=SX126X_SYNC_WORD_PRIVATE,
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power=14, currentLimit=60.0, preambleLength=8, implicit=False, implicitLen=0xFF,
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crcOn=True, txIq=False, rxIq=False, tcxoVoltage=1.6, useRegulatorLDO=False,
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blocking=True):
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state = super().begin(bw, sf, cr, syncWord, currentLimit, preambleLength, tcxoVoltage, useRegulatorLDO, txIq, rxIq)
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ASSERT(state)
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if not implicit:
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state = super().explicitHeader()
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else:
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state = super().implicitHeader(implicitLen)
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ASSERT(state)
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state = super().setCRC(crcOn)
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ASSERT(state)
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state = self.setFrequency(freq)
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ASSERT(state)
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state = self.setOutputPower(power)
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ASSERT(state)
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state = super().fixPaClamping()
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ASSERT(state)
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state = self.setBlockingCallback(blocking)
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return state
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def beginFSK(self, freq=434.0, br=48.0, freqDev=50.0, rxBw=156.2, power=14, currentLimit=60.0,
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preambleLength=16, dataShaping=0.5, syncWord=[0x2D, 0x01], syncBitsLength=16,
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addrFilter=SX126X_GFSK_ADDRESS_FILT_OFF, addr=0x00, crcLength=2, crcInitial=0x1D0F, crcPolynomial=0x1021,
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crcInverted=True, whiteningOn=True, whiteningInitial=0x0100,
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fixedPacketLength=False, packetLength=0xFF, preambleDetectorLength=SX126X_GFSK_PREAMBLE_DETECT_16,
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tcxoVoltage=1.6, useRegulatorLDO=False,
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blocking=True):
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state = super().beginFSK(br, freqDev, rxBw, currentLimit, preambleLength, dataShaping, preambleDetectorLength, tcxoVoltage, useRegulatorLDO)
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ASSERT(state)
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state = super().setSyncBits(syncWord, syncBitsLength)
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ASSERT(state)
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if addrFilter == SX126X_GFSK_ADDRESS_FILT_OFF:
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state = super().disableAddressFiltering()
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elif addrFilter == SX126X_GFSK_ADDRESS_FILT_NODE:
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state = super().setNodeAddress(addr)
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elif addrFilter == SX126X_GFSK_ADDRESS_FILT_NODE_BROADCAST:
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state = super().setBroadcastAddress(addr)
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else:
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state = ERR_UNKNOWN
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ASSERT(state)
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state = super().setCRC(crcLength, crcInitial, crcPolynomial, crcInverted)
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ASSERT(state)
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state = super().setWhitening(whiteningOn, whiteningInitial)
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ASSERT(state)
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if fixedPacketLength:
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state = super().fixedPacketLengthMode(packetLength)
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else:
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state = super().variablePacketLengthMode(packetLength)
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ASSERT(state)
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state = self.setFrequency(freq)
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ASSERT(state)
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state = self.setOutputPower(power)
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ASSERT(state)
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state = super().fixPaClamping()
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ASSERT(state)
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state = self.setBlockingCallback(blocking)
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return state
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def setFrequency(self, freq, calibrate=True):
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if freq < 150.0 or freq > 960.0:
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return ERR_INVALID_FREQUENCY
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state = ERR_NONE
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if calibrate:
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data = bytearray(2)
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if freq > 900.0:
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data[0] = SX126X_CAL_IMG_902_MHZ_1
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data[1] = SX126X_CAL_IMG_902_MHZ_2
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elif freq > 850.0:
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data[0] = SX126X_CAL_IMG_863_MHZ_1
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data[1] = SX126X_CAL_IMG_863_MHZ_2
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elif freq > 770.0:
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data[0] = SX126X_CAL_IMG_779_MHZ_1
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data[1] = SX126X_CAL_IMG_779_MHZ_2
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elif freq > 460.0:
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data[0] = SX126X_CAL_IMG_470_MHZ_1
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data[1] = SX126X_CAL_IMG_470_MHZ_2
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else:
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data[0] = SX126X_CAL_IMG_430_MHZ_1
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data[1] = SX126X_CAL_IMG_430_MHZ_2
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state = super().calibrateImage(data)
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ASSERT(state)
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return super().setFrequencyRaw(freq)
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def setOutputPower(self, power):
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if not ((power >= -9) and (power <= 22)):
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return ERR_INVALID_OUTPUT_POWER
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ocp = bytearray(1)
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ocp_mv = memoryview(ocp)
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state = super().readRegister(SX126X_REG_OCP_CONFIGURATION, ocp_mv, 1)
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ASSERT(state)
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state = super().setPaConfig(0x04, _SX126X_PA_CONFIG_SX1262)
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ASSERT(state)
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state = super().setTxParams(power)
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ASSERT(state)
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return super().writeRegister(SX126X_REG_OCP_CONFIGURATION, ocp, 1)
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def setTxIq(self, txIq):
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self._txIq = txIq
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def setRxIq(self, rxIq):
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self._rxIq = rxIq
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if not self.blocking:
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ASSERT(super().startReceive())
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def setPreambleDetectorLength(self, preambleDetectorLength):
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self._preambleDetectorLength = preambleDetectorLength
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if not self.blocking:
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ASSERT(super().startReceive())
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def setBlockingCallback(self, blocking, callback=None):
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self.blocking = blocking
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if not self.blocking:
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state = super().startReceive()
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ASSERT(state)
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if callback != None:
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self._callbackFunction = callback
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super().setDio1Action(self._onIRQ)
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else:
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self._callbackFunction = self._dummyFunction
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super().clearDio1Action()
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return state
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else:
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state = super().standby()
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ASSERT(state)
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self._callbackFunction = self._dummyFunction
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super().clearDio1Action()
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return state
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def recv(self, len=0, timeout_en=False, timeout_ms=0):
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if not self.blocking:
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return self._readData(len)
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else:
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return self._receive(len, timeout_en, timeout_ms)
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def send(self, data):
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if not self.blocking:
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return self._startTransmit(data)
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else:
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return self._transmit(data)
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def _events(self):
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return super().getIrqStatus()
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def _receive(self, len_=0, timeout_en=False, timeout_ms=0):
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state = ERR_NONE
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length = len_
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if len_ == 0:
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length = SX126X_MAX_PACKET_LENGTH
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data = bytearray(length)
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data_mv = memoryview(data)
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try:
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state = super().receive(data_mv, length, timeout_en, timeout_ms)
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except AssertionError as e:
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state = list(ERROR.keys())[list(ERROR.values()).index(str(e))]
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if state == ERR_NONE or state == ERR_CRC_MISMATCH:
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if len_ == 0:
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length = super().getPacketLength(False)
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data = data[:length]
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else:
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return b'', state
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return bytes(data), state
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def _transmit(self, data):
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if isinstance(data, bytes) or isinstance(data, bytearray):
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pass
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else:
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return 0, ERR_INVALID_PACKET_TYPE
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state = super().transmit(data, len(data))
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return len(data), state
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def _readData(self, len_=0):
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state = ERR_NONE
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length = super().getPacketLength()
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if len_ < length and len_ != 0:
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length = len_
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data = bytearray(length)
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data_mv = memoryview(data)
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try:
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state = super().readData(data_mv, length)
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except AssertionError as e:
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state = list(ERROR.keys())[list(ERROR.values()).index(str(e))]
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ASSERT(super().startReceive())
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if state == ERR_NONE or state == ERR_CRC_MISMATCH:
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return bytes(data), state
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else:
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return b'', state
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def _startTransmit(self, data):
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if isinstance(data, bytes) or isinstance(data, bytearray):
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pass
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else:
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return 0, ERR_INVALID_PACKET_TYPE
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state = super().startTransmit(data, len(data))
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return len(data), state
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def _dummyFunction(self, *args):
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pass
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def _onIRQ(self, callback):
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events = self._events()
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if events & SX126X_IRQ_TX_DONE:
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super().startReceive()
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self._callbackFunction(events)
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